Differential Amplifier Design
Note
The underlying theory about current mirrors etc is skipped but might be added at some point.
Intro to Differential Amplifier Design
Differential amplifiers amplify a voltage difference at the input and are fundamental circuits in electronics. They are used in operational amplifier circuits and when ever a differential signal need to be amplified. Differential signals do have the advantage that they are immune to crosstalk and noise as those influence have no impact on the difference of this voltage levels. see SRAM technology.
fig1
The principle is that a rising 
will reduce the voltage at 
. This will reduce the voltage over 
and will lead to a lower current in the right path which is causing 
to increase. We need a Resistor 
to make sure that both Transistors stay in Saturation Region.
Key Parameters
Gain
The Overall gain consists of 2 parts, the differential gain 
and the Common mode gain 
. Since we are interested to build up an differential amplifier, the common mode gain should be as small as possible.
The differential gain defines how much the voltage difference between and 
will be amplified whereas the common mode gain amplifies the input voltages itself (what we don't want to happen):
Common Mode Amplification
We can calculate the amplification if we connect both input pins together. As both Transistors and Resistors now work in parallel they the resistance is half of the original value whereas the transistors become twice as strong which means that we can double the Width/Length ratio.
fig2
As you can see this is now a common Source stage.
The gain for a CS stage is
from which we can derive the formula for our amplification.
You can see from that equation that an infinite would lead to no common mode amplification as it would be an ideal current source.
Input Common Mode Range
As it had been discussed above the amplifier just works around an operating point. The range in which the amplifier works is defined as input common mode range (ICMR). We have linear dependency between the output voltages until one of the transistors leaves saturation. The INput common mode range is ~ 50% of 
Offset
Transistors are not ideal because of several reasons during manufacturing therefore an 2 equal input values must not result in equal output voltages. We therefore add an Offset Voltage 
to compensate this problem. is usually in the range of 5-20mV.
Real amplifiers
In real live the difference of the input voltages is amplified and a voltage which is proportional to this difference is generated.
fig3
Note that 
is limited to 
as upper bound and 
as lower bound.
We also want to be able to amplify "negative" voltages, therefore we lower to a negative value. We can achieve the same effect by adding an offset to the input voltages. However, if we do so we generate a new reference voltage, analogue ground which is 0V and in the middle between and .
Making it single ended
We could change the circuit from fig1 in such a way that we just ignore one of the output voltage. The Problem with that is that both output voltages "move" in the opposite direction when the input voltage difference changes. By losing one of this voltages the gain would drop by 50%.
A better solution is to use a current mirror as pull up network.
fig4
Lets say is rising:
The current in 
( 
) is increasing while the current in 
( 
) is decreasing by the same value.
But at the same time the voltage over 
is decreasing which is pulling gate node of the current mirror to ground. This will cause the currents in and 
to get bigger which is also causing the output voltage to rise.
Also you can see that I have replaced by a NMOS. The reason is that resistors are difficult to manufacture on a chip. The bias voltage 
determines the "resistance" of this pull down network.
Calculations
The current in 
is the sum of the currents that go through and
gain
The small signal gain may be obtained from
where 
is the transconductance of the differential inputs.
where 
is determined my the and
we obtain (explanation on factors might be added in the future)
Input Voltage Range
As mentioned earlier and need to be in saturation, therefore the input voltages need to be in a certain range.
Investigation:
sweep the common mode voltage (inputs connected) [will be simulated later]
We have to find the highest and lowest possible input voltage for which and are in saturation.
For a single transistor we know that we need to fulfill 
to be in saturation region (and 
of course)
Maximum voltage
The maximum common mode voltage is the same as the gate voltage at . It is minus the voltage drop over Source to gate plus the threshold voltage of .
Minimum voltage
determines the minimum voltage as also has to stay in saturation.
Slew Rate
The Slew rate determines how fast the output can charge or discharge a capacitive load 
at the output . All internal parasitic contribute of course also to the Slew rate. However, defines this attribute
3dB-frequency
We dither a constant input voltage (which is inside the ICMR) with a AC voltage. The 3dB frequency is the frequency of the AC voltage at which the output signal of this AC is only 70% percent. It is determined by the output resistance.
Power dissipation
The power consumption is the voltage drop over the full circuit times the current in
Example Design
This example will be based on a 0.8µm Technology for which we have
| Parameter | Description | NMOS | PMOS | Unit |
 |
Threshold Voltage |  |
 |
 |
 |
Transistor-Transconductance |  |
 |
 |
 |
Bodyfactor |  |
 |
 |
 |
Channel-length-modulation factor |   |
|
 |
 |
Surface potential for strong inversion |
 |
|
|
Design Targets
Supply Voltage:
Slew Rate:
3dB frequency
Input common mode range
Differential Amplification
Power Dissipation
Calculation
The Slew Rate tells us how fast the load need to be charged/uncharged. As is given (5pF) we can calculate the minimum current 
(note that the Slew rate is given as Volts per µs and therefore needs to be multiplied)
The Power dissipation 
is giving us the upper bound for
If we also take the channel length modulation factors into consideration we have
And by having knowledge about the 3dB frequency we can calculate 
With knowledge about we can set a lower bound which is considering the channel length modulation factor.
We now know 
To have some margin we set 
.
Designing the current mirror (ICMR max)
We need to determine the saturation current of (and therefore also ) to make sure that we have half of 
balanced on each side 
we know that
therefore
Now we can determine the size of and , the current is
Note that this is an PMOS device and that 
Designing the Pull down transistors M1 and M2
From the gain specification and from the knowledge about the currents we now can calculate the W/L ratio for M1 and M2.
M5
From the ICMR we can calculate 
We first need to know 
W/L ratio for 
for bias current mirror
Simulation
I use LTSPICE for the simulation.
Offset and transfer
First I want to check if the offset voltage and the transfer characteristics.
We set the negative input to analog 0V and sweep the positive input.
**differential amplifier offset and transfer characteristics *voltages VIN+ 1P 0 DC 1.65 VDD 1 0 DC 3.3 VIN- 1M 0 DC 1.65 *load CL 3 0 5P *transistors M3 2 2 1 1 MODP W = 833.3U L = 10U M4 3 2 1 1 MODP W = 833.3U L = 10U M1 2 1P 5 0 MODN W = 1645.7U L = 10U M2 3 1M 5 0 MODN W = 1645.7U L = 10U M5 5 7 0 0 MODN W = 822.9U L = 10U *current mirror for bias M6 7 7 0 0 MODN W = 822.9U L = 10U RR 1 7 13160 *transistor specs .MODEL MODN NMOS VTO=0.5 KP=175U GAMMA=0.58 LAMBDA=0.06 PHI = 0.8 .MODEL MODP PMOS VT0=-0.65 KP=60U GAMMA=0.42 LAMBDA=0.06 PHI = 0.8 .DC VIN+ 0.0 3.3 50U .END
Plot 1 V(3)
From the plot you can see that the supply voltage range is used from 0,9V to 3,1V
We do have an offset but as we are in the linear region this can be fixed by adding an offset voltage of about 3,5mV to the negative input.
It also can be seen that a 0,001V change of the input voltage results in a 0,2V difference at the output, so we have met our design goal for an Amplification factor of 200.
ICMR with unity gain configuration
Not we want to check the range of operation if we connect the output to the negative input and sweep the positive input.
**ICMR with unity gain configuration *voltage VIN+ 1P 0 DC 1.65 VDD 1 0 DC 3.3 *load CL 3 0 5p *transistors *dif ampf M3 2 2 1 1 MODP W=833u L=10u M4 1M 2 1 1 MODP W=833u L=10u M1 2 1P 5 0 MODN W=1645u L=10u M2 1M 1M 5 0 MODN W=1645u L=10u M5 5 7 0 0 MODN W=822u L=10u *current mirror M7 7 7 0 0 MODN W=822u L=10u RR 1 7 13.166k *transistor specs .MODEL MODN NMOS VTO=0.5 KP=175U GAMMA=0.58 LAMBDA=0.06 PHI = 0.8 .MODEL MODP PMOS VT0=-0.65 KP=60U GAMMA=0.42 LAMBDA=0.06 PHI = 0.8 *input sweep .dc VIN+ 0.0 3.3 50u .END
We can see that we have met our design goal of
Bode Plot
In this configuration we want to see at which frequency the AC is not amplified anymore.
**bode plot *voltages VIN+ 1P 0 DC 1.65 AC 1.0 VDD 1 0 DC 3.3 VIN- 1M 0 DC 1.65 *load CL 3 0 5P *transistors M3 2 2 1 1 MODP W = 833.3U L = 10U M4 3 2 1 1 MODP W = 833.3U L = 10U M1 2 1P 5 0 MODN W = 1645.7U L = 10U M2 3 1M 5 0 MODN W = 1645.7U L = 10U M5 5 7 0 0 MODN W = 822.9U L = 10U *current mirror for bias M6 7 7 0 0 MODN W = 822.9U L = 10U RR 1 7 13160 *transistor specs .MODEL MODN NMOS VTO=0.5 KP=175U GAMMA=0.58 LAMBDA=0.06 PHI = 0.8 .MODEL MODP PMOS VT0=-0.65 KP=60U GAMMA=0.42 LAMBDA=0.06 PHI = 0.8 .AC DEC 50 1 100MEG .PRINT AC V(3) .END
Plot 3 Bode Diagram
We have a -3dB frequency of around 355kHz which is better that the requirement of 200kHz so we also met this criteria.
Slew Rate
How fast can the capacitive load be charged and uncharged?
**Slew Rate *voltage VIN+ 1P 0 PWL (0.0 1.0, 0.2U 1.0, 0.20001U 2.0, 0.8U 2.0, 0.80001U, 1.0) VDD 1 0 DC 3.3 *load CL 1M 0 5p *transistors *dif ampf M3 2 2 1 1 MODP W=833u L=10u M4 1M 2 1 1 MODP W=833u L=10u M1 2 1P 5 0 MODN W=1645u L=10u M2 1M 1M 5 0 MODN W=1645u L=10u M5 5 7 0 0 MODN W=822u L=10u *current mirror M7 7 7 0 0 MODN W=822u L=10u RR 1 7 13.166k *transistor specs .MODEL MODN NMOS VTO=0.5 KP=175U GAMMA=0.58 LAMBDA=0.06 PHI = 0.8 .MODEL MODP PMOS VT0=-0.65 KP=60U GAMMA=0.42 LAMBDA=0.06 PHI = 0.8 .tran 0 1u .PRINT TRAN V(1P) V(1M) .plot V(3) .END
We can see that the leading and the trailing edge need ~30ns to reach the desired voltage, the slew rate therefore is (the 
is needed to bring it to the 
scale
so also the slew rate is better than our requirement.